1. Field of the Invention
The invention relates generally to methods and apparatus for improving data rates in computer systems having a dual bus architecture, i. e., in computer systems having a first bus included in a System Bus Master (for example, the local bus on the system processor card or complex), and a second bus for coupling an Alternate Bus Master (and typically other devices as well) to the first bus. More particularly, the invention relates to methods and apparatus for improving data rates to/from a processor card's dynamic random access memory (DRAM) subsystem during Alternate Bus Master initiated memory cycles, including a plurality of memory cycles required to support burst mode data transfers, over each of the aforesaid buses and over the interface between the two buses.
2. Description of the Related Art
Commercially available high performance industrial computing systems, such as the IBM System 7568 ("IBM" is a trademark owned by the International Business Machines Corporation), are well known by those skilled in the art. Such systems are typically designed to function without operator attendance in extreme environments, are easy to maintain and have the dual bus structure referred to hereinabove.
In the IBM System 7568, briefly described hereinafter for background purposes only, circuit cards are packaged in individual shrouds that are plugged into a passive backplane. The backplane provides power to the attached cards and provides a card to card communication bus (an example of the "second" bus referred to hereinbefore) which, in the illustrative IBM System 7568, is referred to as a Micro Channel bus ("Micro Channel" is a trademark owned by the International Business Machines Corporation).
The invention will, for the sake of illustration only, be set forth hereinafter with reference to the dual bus Micro Channel architecture found in computers such as the IBM System 7568. Those skilled in the art will readily appreciate that the IBM Micro Channel bus is an example of the more general class of card to card type communication buses found in dual bus architectures in which the invention may be advantageously used. Accordingly, although the well known IBM dual bus Micro Channel architecture serves as a vehicle for illustrating the principles of the invention and will be used as such herein, it is not intended that the invention be limited to use in IBM dual bus Micro Channel systems per se.
The base system for the 7586 consists of a processor card and a system resource card. These two cards provide the function of a well known IBM PS/2 planer board ("PS/2" is a trademark owned by the International Business Machines Corporation). The system resource card contains the system interfaces for video, keyboard, diskette, and configuration information stored in low power CMOS memory. The processor card contains the microprocessor, math coprocessor (or other floating point unit), and base memory with error correction code (ECC). Communications between the microprocessor and the base memory take place over a local on card bus (an example of the "first" bus referred to hereinabove). In the IBM system 7586 the microprocessor is an Intel 80386 ("Intel" is a trademark owned by Intel Corporation).
Although the invention to be described hereinafter may be implemented in an 80386 based system, those skilled in the art will readily appreciate that more advanced microprocessors are presently being introduced, such as the Intel 80486 processor. Accordingly, the timing information discussed in developing the background of the invention will be referenced to the 80486, though the particular processor utilized in conjunction with the invention is not intended to be an invention limiting factor.
Timing in the 80486, and its associated DRAM subsystem, is based upon a 25 MHz clock or 40 ns period. Minimum microprocessor cycle time is 80 ns during which the 80486 first sets up addressing (in one 40 ns period) and then looks for data (in the second 40 ns period).
Additional time, or wait states, can be added to the 80 ns microprocessor cycle by, for example, use of a device ready signal. A 40 ns wait state would be a natural cycle extension increment for systems utilizing a 25 MHz clock.
In systems such as the illustrative IBM System 7568, the interface to resources located on the processor card by an Alternate Bus Master is provided through a Micro Channel Arbitration Process (or more generally through the arbitration process associated with whatever card to card type communications bus is used in a given dual bus system), resident on the aforementioned system resource card. Such process, and indeed the Micro Channel structure itself, are described in many publications, including the technical reference manual for the IBM System 7568. The description of the Micro Channel Arbitration Process, the Micro Channel structure and related signalling, all set forth in the IBM System 7586 technical reference manual, is hereby incorporated by reference.
In accordance with the teachings of the aforementioned reference, after the arbitration process has established an Alternate Bus Master as the Micro Channel bus owner, the Alternate Bus Master is allowed to request a transaction to or from processor memory. By default, as taught in the reference, only one Micro Channel device can own the Micro Channel bus at any given point in time.
The aforementioned memory request may be managed via a well known system hold (SHOLD) and system hold acknowledge (SHOLDA) handshaking technique. The details of a basic process which may be used to provide the aforementioned (or similar) handshaking capability, is described in Intel documentation supporting the 80486 processor, such as the i486 Microprocessor Hardware Reference Manual, hereby incorporated by reference ("i486" is a trademark owned by Intel Corporation). A similar handshaking capability could, for example, include a local bus access request/acknowledgement procedure and request/acknowledgement techniques in general.
SHOLD is a signal generated on the processor card itself based on an address decode where the address is provided to the processor by the Alternate Bus Master via the Micro Channel bus/processor interface. More particularly, as will be explained hereinafter in the Detailed Description of the invention, the SHOLD signal results from the Alternate Bus Master driving certain processor control signals via the Micro Channel bus to signal the start of an Alternate Bus Master controlled data transfer.
Functionally, the SHOLD signal is a request for the processor card to relinquish its on card bus (the Micro Channel bus is already owned by the Alternate Bus Master following the aforementioned arbitration process), in order to allow an external cycle to take place. According to the prior art SHOLD/SHOLDA handshaking scheme, the on card processor bus is not relinquished until the processor acknowledges the SHOLD request with the SHOLDA signal. The SHOLDA signal will always be generated in response to an SHOLD signal; however, the timing of the SHOLDA signal may vary based, for example, on processor activity in progress when the SHOLD signal is generated (e.g., a memory refresh or other local bus memory access).
According to techniques utilized in the exemplary IBM System 7568, the SHOLDA signal (which stays on card) indicates the start of an on card transfer of data to or from the local bus. The actual "handshake" signal back to the Alternate Bus Master takes the form of another control signal, sent over the Micro Channel interface (to be described in more detail hereinafter), which indicates that the on card data transfer to or from the local bus is complete.
Those skilled in the art will recognize, in the context of a dual bus system architecture, that during an Alternate Bus Master Micro Channel granted cycle the processor card is not restricted from conducting local on card cycles both from central processing unit (CPU) cache memory and the processor's on card memory (in particular, DRAM).
This prior art capability of allowing multi-device accesses to system resources (such as DRAM) may on the one hand be used to enrich the system processing power; but is often achieved at the expense of making optimal use (in terms of data transfer rate) of other system resources, such as the Micro Channel structure in a dual bus architecture. In view of this problem, it would be desirable, in computing systems having a dual bus structure, to optimize and in some sense balance the use of resources located on the processor card with the use of other system resources, such as a Micro Channel bus and devices attached thereto.
As an example of what is desirable, given the mutually exclusive bus structures in a dual bus system, the CPU should be able to execute instructions from its cache memory as well as across its own (local) bus in the most efficient manner possible without unduly degrading the performance of the Micro Channel bus interfacing with the local bus. The need for the processor to have this capability is well recognized in situations where (1) DRAM refresh requests need to be serviced; (2) the processor needs to fill its instruction prefetch queue from DRAM without losing time waiting for the availability of its local bus; and (3) the processor is operating out of cache memory and/or needs to access DRAM, etc. Accordingly, whenever the processor is put into a "HOLD" state by an Alternate Bus Master, it should be "held up" in a manner that is both timely and productive when looking at the system as a whole.
In the present commercially available version of the IBM System 7586, the 80386 processor card is implemented such that the local bus is relinquished to the processor after each memory cycle. Another SHOLD/SHOLDA handshake sequence is required for each successive processor card/local bus cycle required by the Alternate Bus Master. This methodology was designed to insure that the CPU would have the right to hold off the oncoming Alternate Bus Master in order to conduct a memory refresh, code fetch or data access to continue operation. This prior art technique proved to be an efficient way to optimize the CPU (local) bus; however, the efficiency of the Micro Channel bus could be severely degraded during Alternate Bus Master possession.
As an example, if a typical local bus memory cycle via the Micro Channel bus requires 400-500 ns, and a handshake sequence is required for each transfer over the Micro Channel bus, an overhead expenditure on the order of 1 microsecond is required for each and every transfer across the Micro Channel bus assuming a 500-600 ns handshake interval. Those skilled in the art will readily appreciate that such time demands can rapidly degrade the performance of the Micro Channel bus, particularly where a burst transfer sequence requiring many cycles is utilized to perform an Alternate Bus Master data transfer.
"Burst" mode transfers referred to herein contemplate the need for intensive/long streams of data passing along the Micro Channel bus to/from CPU on card memory. An example of a well known Alternate Bus Master which utilizes burst type transfers to efficiently move data across the Micro Channel bus interface with a processor card includes bursting direct memory access (DMA) type devices responsible for a direct access storage device (DASD) subsystem.
During, for example, the loading of an operating system, the performance of file management operations, etc., a DASD subsystem Alternate Bus Master may be required to transfer millions of bytes of information which, according to the known dual bus management techniques, would require repetitive handshaking in order to manage the tasks of data transfer per se, memory refresh management, instruction prefetch queue memory access, etc.
It should be noted that the prior art dual bus management techniques implemented utilizing the aforementioned handshaking scheme have the potential to degrade Micro Channel bus performance in other situations as well.
For example, the use of the handshaking method was perceived as a way to provide a memory refresh cycle to on card memory as soon as a channel ready return signal "CHRDYRTN" (explained in detail in the incorporated Micro Channel architecture oriented publication) was given for the previous Alternate Bus Master cycle, by not responding to the next command from the Alternate Bus Master so long as the SHOLDA line was pulled low (inactive) by the processor during a refresh request. This refresh request cycle was handled while the off card Alternate Bus Master was still in control of the Micro Channel bus.
As such, another problem with the prior technique for managing the dual bus structure occurs if an extended SHOLDA low state (inactive) persists while the Alternate Bus Master has already started the beginning of a command cycle. In this situation, even if a master of higher priority is preempting for the Micro Channel bus, the currently executing master will not be able to exit the channel until the original command has been serviced by the CHRDYRTN signal, further stalling the Micro Channel bus.
Accordingly, it would be desirable to be able to provide an Alternate Bus Master bursting data rate management technique, for use in dual bus systems, which achieves a balance between the need for optimizing the use of the system processor and its associated resources (such as DRAM) and Alternate Bus Master/Micro Channel bus efficiency, with the overall objective of reducing the overhead associated with data transfers generally, and more particularly with the object of reducing the overhead associated with burst mode data transfers.
Furthermore, it would be desirable to provide dual bus management techniques which are not prone to unduly stalling the card to card communications bus (such as the IBM Micro Channel bus) as a result of performing required memory refresh operations, etc.
Still further, it would be desirable to provide methods and apparatus, for managing the interface between a local processor bus and a Micro Channel bus which (1) take into account the necessity of having to promptly service pending memory refresh requests; (2) limit multiple Alternate Bus Master accesses to on card memory to a predetermined (but potentially programmable) number of cycles in situations where the processor is requesting the use of its local on card memory bus; and (3) allow an Alternate Bus Master unlimited accesses to on card memory in situations where the Alternate Bus Master owns the Micro Channel bus and the system processor subsequently requests the Micro Channel bus. Such methods and apparatus, as will be demonstrated hereinafter, may be utilized to achieve the desired optimal use of system resources and balance of performance (in terms of data rate) between the system processor and a Micro Channel type bus in computer systems having a dual bus structure.